Digital phase-correcting servo for controlling the phase of an analog drive signal

ABSTRACT

An analog drive signal for driving a vibrator, motor, or like driven apparatus, is converted to a digital signal and is delayed in a digital buffer memory. The memory is unloaded at two separate discrete times and the resulting digital signals are converted to provide an analog reference signal and an analog drive signal. The reference signal is unloaded at a constant rate relative to the input load rate but is displaced in time by a selected number of total memory locations. The drive signal is unloaded at a programmable rate. The phase relation, i.e., error signal, and signals indicative of the lead or lag of the error signal relative to the reference signal, are sensed and any phase difference detected is counted in units of sample rate time and stored. Associated digital control logic is programmed to cause the drive signal to move the detected number of samples in the memory, in the commensurate direction, to correct the phase of the driven apparatus output, i.e., to provide a zero phase difference relative to the phase of the reference signal. The servo may be preset for minimum initial phase shift by noting the maximum error at the beginning of a test sweep, and by presetting the system correspondingly to start it in phase.

United States Patent [72] Inventor John T. Bobbitt Houston, Tex.

[2i 1 Appl. No. 87,390

[22] Filed Nov. 6, 1970 [45] Patented Dec. 7, I97I [73] Assignee MandrelIndustries, Inc.

Houston, Tex;

[54] DIGITAL PHASE-CORRECTING SERVO FOR CONTROLLING THE PHASE OF ANANALOG Primary E.mminer- Benjamin Dobeck Attorney-Robert Gr ClayABSTRACT: An analog drive signal for driving a vibrator, motor, or likedriven apparatus, is converted to a digital signal and is delayed in adigital buffer memory. The memory is unloaded at two separate discretetimes and the resulting digital signals are converted to provide ananalog reference signal and an analog drive signal. The reference signalis unloaded at a constant rate relative to the input load rate but isdisplaced in time by a selected number of total memory locations. Thedrivesignal is unloaded at a programmable rate. The phase relation,i.e., error signal, and signals indicative of the lead or lag of theerror signal relative to the reference signal, are sensed and any phasedifference detected is counted in units of sample rate time and stored.Associated digital control logic is programmed to cause the drive signalto move the detected number of samples in the memory, in thecommensurate direction, to correct the phase of the driven apparatusoutput, i.e., to provide a zero phase difference relative to the phaseof the reference signal. The servo may be preset for minimum initialphase shift by noting the maximum error at the beginning of a testsweep, and by presetting the system correspondingly to start it inphase.

FIB (PAD) IO l2 OIOITAL PHASE SHIFT UNIT 28 32 34 l6 30 DRIVE IDRIVEsIONAL DRIVEN ANALOG D/A APPARATUS INPUT A/D SE ZSER J 1 (VIBRATOR) RY so iiii EANS REF 22 ACCELEROMETER l4 2O DOUBLE I lNTEGRATOR l I l l I 36l l l I l REFERENCE AUTO, GAIN 2 SIGNAL CONTROL MEMORY LOAO/ I-/ERRORSIGNAL uNLoAO MEANs PHASE LEAD/LAG sENsE SIGNAL DETECTOR I 26 MEANS /38Cams, I MEANS COUNT ENABLE I PATENIED DEC 7 WI SHEET 1 0F 6 mm :23 Kimwm Im 44.205

llll I I l l I INVENTOR. JOHN T. BOBBIT T mumnom wmz A TORNEYPATENIEDBEB 71971 3626267 SHEET 5 [IF 6 wJm/Zm P2300 0 3 mommw INVENTOR.

JOHN T. BOBBITT w/fea ATTORNEY PATENTED DEC 1 m:

SHEET 6 [IF 6 INVENTOR- JOHN T. BOBBITT mi mJmdzm mmwmood muzwmwuwm IIIll l ATTORNEY L BE I Ill wwifii ii I I I I I I h I l. J @8181 1 I 9:3 5E052 oh r|||.H I W w w c m m- IMIHIHi I JIM x DIGITAL PHASE-CORRECTINGSERVO FOR CONTROLLING THE PHASE OF AN ANALOG DRIVE SIGNAL BACKGROUND OFTHE INVENTION 1. Field The invention relates to a circuit forautomatically controlling the phase of a driven apparatus such as, forexample, a hydraulic vibrator, to within a selected number of degreesand with a correction rate limited only by the vibrator response time.Although particularly described with respect to a hydraulic vibrator forgenerating seismic signals, it is understood that the invention may beutilized for correcting the phase of any analog drive signal for usewith a variety of driven apparatus.

2. Prior Art Previous systems for controlling vibrators such as thehydraulically actuated vibrators employed in the generation of seismicsignals, provide analog phase control requiring three to five cycles ofsignal time to develop control sense. Such analog systems furtherprovide very poor phase lock at low frequencies, and poor recovery ofcontrol upon the occurrence of transient interruptions.

Further, analog control systems inherently provide overcorrection of anerror in phase in an output signal, since the analog control systemitself is a reactive component much in the same manner as the drivenapparatus. This overcorrection tends to cause oscillation, i.e,,hunting." In fact, various analog control systems provide slowercompensation than the driven apparatus itself. In addition, analogcontrol systems can only provide control of the driven apparatus duringthe presence of the error signal, and cannot provide control at suchtime as the error is no longer available.

SUMMARY OF THE INVENTION The present invention provides a digital phasecorrecting servo which utilizes a digital memory to provide phasecorrection for an analog drive signal. Unlike analog servos, theinvention digital servo experiences no overcorrection effects at thememory since the latter is not a reactive component.

To this end, the analog drive signal (sweep signal as utilized herein byway of example only) is converted to a digital signal, which in turn isstored in a digital buffer memory with a minimum capacity large enoughto store one cycleat the lowest frequency of concern (5 hertz in thisexample). The memory is unloaded at two separate discrete times and theresulting signals are converted back to two separate analog signals. Onesignal is unloaded at a constant rate relative to the input load rate,but displaced in time by one-half of the total memory locations. Thissignal is used as a reference signal. The other signal is unloaded at aprogrammable rate and is used to drive the driven apparatus.

The output of the driven apparatus (e.g. vibrator) is sampled and iscompared to the reference signal to determine the phase relationship andany time difference detected is counted in units of sample rate time.Lead or lag in the phase of the vibrator output relative to thereference signal is also sensed and digital control logic is programmedto cause the drive signal to be moved the detected number of samples inthe memory in the proper direction, to correct the operation of thedriven apparatus such that its output has a zero phase dif-v ferencerelative to the reference signal to which it is .being compared.

The phase error between the driven apparatus signal and;

the reference signal is sensed. by a phase detector means, whichdelivers a signal indicative of the error to a level detector means. Thelevel generated by the level detector means determines the output of aprogram matrix means. The latter means in turn determines the countingrate of an associated variable sample rate counter and associated logicmeans, i.e., determines the rate of correction of any phase error in thedrive signal. A lead/lag signal is also provided by the phase detectormeans which determines whether the variable sample rate counter speedsup or slows down. The counter and associated logic means controls thedigital memory to move the drive signal the detected number of samplesto correct the output of the driven apparatus and thus provide a zerophase difference between it and the reference signal.

The phase detector means inherently provides a phase error signal onlyat the crossover points. Accordingly an error count and register meansis provided to count the error in units of memory samples, and to storethe information. Correction of phase error is then made via the phasedetector means, the level detector means, the programmatrix means, thevariable sample rate counter and associated logic means, over the entireinterval rather than only during the presence of the error signal.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a simplified block diagramof the invention digital servo as employed in a seismic vibrator system.

FIG. 2 is a more detailed block diagram of one embodiment of theinvention of FIG. 1.

FIG. 3, 4, 5 and 6 are schematic diagrams of the various logiccircuitsshown in block form in FIG. 2, illustrating in further detaillogic which may be utilized in accordance with the invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG. 1, there isshown a digital phase correcting servo 10 in accordance with theinvention, as employed to control and correct the phase of ananalogdrive signal initially generated as an analog input signal by ananalog signal source 12. The drive signal from the digital phasecorrectingservo I0 is fed to a driven apparatus 14 via a drive amplifier16. For simplicity of presentation the driven apparatus 14 is hereindepicted as a hydraulically actuated vibrator, conventionally utilizedfor generating seismic signals in geophysical exploration processes. Theoutput of a vibrator (or driven apparatus) variesjn phase, relative toits input, with frequency, and thus the invention contemplates digitalmeans for maintaining a constantly phased output with changing frequencyby comparing the output to a reference and shifting the phase of theinput the proper amount to correct the phase error. The vibrator I4employs a pad 18 which is securely coupled to the ground toprovideefiicient coupling of the generated energy from the vibrator tothe ground. An accelerometer 20 is secured to the pad and provides meansfor generating a signal indicative of the movement of the pad [B andthus of the analog signal generated. The signal from the accelerometer20 is introduced to a double integrator circuit 22, which convertsacceleration to amplitude and provides an output representative of thedisplacement of the pad 18. The displacement signal is fed into anautomatic gaincontrol means 24 which provides an error" signal havingessentially a constant amplitude, and which contains any phase errors inthe vibrator output. The signal from the automatic gain control means 24is commonly termed an error signal, although it is actually the outputof the vibrator in terms of displacement thereof.

The error signal containing any phase errors of the vibrator 14 outputrelative to the analog input signal delivered by the source12,,is-introduced to the analog phase correcting servo l0 andparticularly to phase detector means 26 thereof. The analog input signalfrom the source 12 is delivered to a digital phase shift unit 28 of theservo l0, and more particularly to an analog to digital (AID) converter30. The analog input signal delivered b source 12 is herein termed aswee si nal, and

the Ampex Corporation ASM 4000. The digital signal is thus stored andsuitably delayed in the memory means 32, which has a minimum capacitylarge enough to store one cycle at the lowest frequency of concern. Inthis particular application by way of example only, the lowest frequencyis of the order of 5 hertz. The memory means 32 provides two outputsignals which are introduced to respective digital-to-analog (D/A)converters 34, 36. The D/A converter 34 provides an analog drive signalto the vibrator 14 via the drive amplifier 16. The reference D/Aconverter 36 provides an analog reference signal which is unloaded at aconstant rate relative to the input load rate to the memory means 32,but which is'displaced in time by one-half of the total memory locations(in this particular application). The reference signal thus representsthe analog input signal. The reference signal is introduced to the phasedetector means 26. The drive signal is unloaded from the memory means 32at a programmable rate commensurate with the desired rate of phase errorcorrection, as further described below.

The phase detector means 26 compares the phase of the incoming error andreference signals at the signal crossover points, i.e., every 180, andanytime difference detected is reflected as a series of pulses having awidth proportional to the magnitude of the phase error. This errorsignal is fed to a digital clock control means 38. A signal indicativeof the lead or lag of the phase of the error signal in relation to thereference signal, is also sensed by the phase detector means 26 and isintroduced to the digital clock control means 38. The clock controlmeans 38 provides a programmed output which drives a memory load/unloadmeans 40 associated with the digital phase shift unit 28. The signalfrom the memory load/unload means 40 is indicative of the rate ofcorrection of the phase error in discrete percent levels, and is thusalso proportional to the magnitude of the phase error of the vibrator14. The signal also reflects the lead or lag of the phase error relativeto the reference signal. Accordingly, the drive signal delivered via thedrive D/A converter 34 is moved the detected number of samples in thememory means 32, in the direction required to correct the vibrator 14output in order to provide a zero phase difference between it and thereference signal from the unit 28.

Referring now to FIG. 2 there is shown in greater detail the digitalphase correcting servo of the present invention. Similar components inthe circuits of FIGS. 1 and 2 are similarly numbered. Accordingly, theerror signal which represents the phase errors in the driven apparatusoutput, is introduced via a terminal 42 to the phase detector 26.Likewise the analog input signal is introduced to the A/D converter viaa terminal 44. The digital signal is introduced to the memory means 32which provides a pair of signal outputs; viz, the drive signal from theD/A converter 34, and the reference signal from the D/A converter 36. Aspreviously noted the drive signal is unloaded from the memory means 32at a programmable rate, and is used to drive the vibrator 14 (FIG. I).The reference signal is unloaded at a constant rate relative to theinput load rate of the memory means 32, but is displaced in time by aselected amount of the total memory locations. In this particularapplication, by way of example only, the reference signal is delayed 128milliseconds, which is onehalf the memory locations of the particularbuffer memory means 32 employed herein. Thus the reference signalrepresents the analog input signal introduced to terminal 44 and is afixed reference. If there is no phase shift in the vibrator outputsignal, no error is sensed by the phase detector 26 and the vibratordisplacement and output signal is in phase with the analog input signal.

Accordingly, the phase detector 26 provides two functions; first, itsenses the lead or lag of the error signal from terminal 42 relative tothe reference signal introduced thereto by the D/A converter 36, andsecond, it delivers a signal representative of the phase error detectedin terms of time, i.e., delivers a series of pulses having a width whichis proportional to the phase error. The phase error output is deliveredto a DC integrator 46, which generates a DC voltage (in the form of aramp) which is proportional to the phase error, that is, provides a DCsignal whose level is proportional to the magnitude of the phase error.The output from the DC integrator 46 is introduced to a DC amplifier 48wherein the signal is amplified and fed to a level detector circuit 50.

The level detector circuit 50 senses the level of the DC signalgenerated by the DC integrator 46 and amplified by the amplifier 48.More particularly, the level detector 50 detects the level of thevoltage at 3 increments along the ramp; a first level A is set at aslight increase from zero (e.g. 5 percent change in frequency of theerror signal). A second level B is set at the mid level (20 percentchange in frequency). A third level C is set at a maximum level (50percent change in frequency). Thus level A provides for a phase errorcorrection rate of 5 percent; the level 8, a correction rate of 20percent; and level C a correction rate of 50 percent. The level detectorcircuit 50 thus provides an output signal on one of three output linesrepresentative of one of the three levels of the ramp generated by theDC integrator 46, which output is introduced to a matrix gates circuit52.

As previously noted the phase detector means 26 also provides a signaltherefrom which is indicative of the lead or lag of the vibrator outputphase relative to the reference signal phase. This lead/lag sense signalis a pulse signal similar to the error signal from the phase detectormeans 26, and provides a low or high level via a switch means (notshown) which is turned on or off. This lead/lag sense signal is alsodelivered to the matrix gates circuit 52, as further described below.

The phase error signal from the phase detector means 26 is alsodelivered as the error up-count enable signal to an error count andregister unit 54. An up clock signal is also introduced to the unit 54and clocks the latter at the basic sample rate of the memory means 32.Thus the error up count enable signal enables the error count andregister unit 54 to count for the duration of the phase error, i.e.,count up until the error pulse ends. The counts are stored in a registerportion of the unit 54, and are equal to the count time of memorylocations in units of memory samples or locations. The units areestablished by the up clock counts which are derived from the samesource which clocks the memory means load counter, described infra. (Thesample rate of the memory means 32 is defined as the time it takes tomove one location to the next location, and is a constant in servo 10.)

Regarding further the function of the error count and register unit 54,the phase detector means 26 senses the phase difference between theerror signal and the reference signal only during the crossover points,i.e., the phase is checked every Accordingly, error information wouldonly be available during the time interval that the error is beingdetected by phase detector 26, or every 180. However, since the unit 54counts the error in terms of memory locations, and stores theinformation, it provides the error count over the entire cycle interval.Phase error correction accordingly can be made over the entire interval,rather than only during the error signal duration.

As previously noted the matrix gates circuit 52 receives two inputs, thelead/lag sense signal from the phase detector 26 and one of the threelevel signals from the level detector circuit 50. If the phase error ofthe vibrator output is leading the condition is indicated by thelead/lag sense signal. The matrix gates circuit 52 enables certain gatestherein in response to the level signal and the lead/lag sense signal,to provide an output on one of seven outputs which is indictive not onlyof the phase error sense (lead or lag), but also of the DC voltage leveldetected by the level detector circuit 50. The latter detennines thephase error rate of correction established by the digital servo.

The matrix gates circuit 52 is coupled to a memory program matrix 56 viaa plurality of output lines (7 in this example), and to aregister-program matrix 58 via a plurality of output lines (3 in thisexample). The latter matrix 58 provides a program output to a variablecorrection rate counter 60, which in turn is coupled to the error countand register unit 54 via a down clock signal. The memory program matrix56 provides a program output to a variable sample rate counter 62 whichin turn is coupled to a drive signal unload counter 64. A basic samplerate counter 66 is connected to a memory load counter 68 and to areference signal unload counter 70. A clock signal is introduced to thevariable sample rate counter 62 and to the basic sample rate counter 66via a terminal 72. The count from the variable sample rate counter 62 issupplied as a clock to the variable correction rate counter 60, whilethe count from the basic sample rate counter 66 is introduced as the upclock signal to the error count and register unit 54, as previouslydescribed.

The counters 64, 68 and 70 provide outputs to an address gates unit 74,which in turn provides the clock signals to the memory means 32. Thesignal from the reference signal unload counter 70 is used to unload thememory means 32 and generate the reference signal, while the drivesignal unload counter 64 unloads the memory means 32 to generate thedrive signal for the vibrator 14.

Accordingly, the memory program matrix 56 provides four basic programsfor programming the variable sample rate counter 62. One is a basicprogram which provides a basic count rate when there is zero phase errorin the vibrator output. The basic program is fed to the variable samplerate counter 62 to clock same at the basic count rate as that of thebasic sample rate counter 66. Three other programs increase the countrate of the variable counter 62 by the correction rate percentagedetermined by the levels generated by the level detector 50. The threeremaining programs decrease the count rate of the variable counter 62 bya similar plurality of correction rate percentages as the three increaseprograms. Thus the memory program matrix 56 provides an output whichdetermines the rate at which the variable counter 62 counts. Whether thecounter 62 counts faster or slower than the basic sample rate counter 66is determined by the lead/lag sense signal delivered to the matrix gatecircuit 52.

The register program matrix 58 comprises a program matrix circuitsimilar to that of matrix 56, and provides a plurality of programs(three in this example) one of which is fed to the variable correctionrate counter 60. The particular program output is determined by thecorrection rate percentage which the level detector circuit 50 andmatrix gates circuit 52 are correcting the phase error. Thus theregister program matrix 58, in conjunction with. the clock fed from thevariable counter 62, provides means for determining how many counts ofthe clock are counted before the variable correction rate counter 60generates a down clock signal, which in turn is fed to the error countand register unit 54 to count down one error count previously storedtherein. Thus the number of counts of the clock before a down clocksignal is fed to the unit 54, is determined by the particular programfed to the variable correction rate counter 60 in response to thecorresponding correction rate level selected by the matrix gate circuit52 in the register program matrix 58.

Accordingly, the memory and register matrix 56, 58 provide essentiallythe same function, e.g., matrix 56 provides a change in the counter 62count rate, while the register pro gram matrix 58 provides a change inthe rate that the error counts are counted down in the error count andregister unit 54.

The count rate introduced from the variable counter 62 to the drivesignal unload counter 64 is either increased or decreased to increase ordecrease correspondingly the speed with which the memory unloads thedrive signal being introduced to the vibrator 14. Accordingly, the speedof the vibrator 14 is increased or decreased to compensate for any phasedifferences detected by the phase detector 26.

The phase error correction process continues until the error count andregister unit 54 counts down to zero, whereupon a zero state clampsignal is sent to the DC integrator to clamp the integrator to aselected DC level. The level detector 50 in turn directs the matrixgates circuit 52 to introduce the basic program to the variable counter62. The counter 62 counts at the same rate as the basic counter 66,indicating no phase error in the vibrator 14 output.

The invention further contemplates the provision of a counter presetmeans 76 coupled to the drive signal unload counter 64. The? procedurefor setting the counter preset means 76 includes generating anddisplaying the phase error, in terms of memory locations or samples, inthe error count and register unit 54. Thus the maximum error at thebeginning of a test sweep survey conducted for just such purpose, asindicated by the register, is noted by the operator. The servo 10 ispreset for minimum initial. phase shift by presetting the drive signalunload counter 64 the indicated number of locations via the counterpreset means 76. Switch means is included for setting the lead or lag ofthe phase error whereby the servo drive signal and thus the vibrator isstarted in phase. The counter preset means 76 is further described infrain FIG. 6.

[t is noted that the circuit of FIG. 2 provides a rather sophisticatedservo which includes a plurality of programs for tailoring thecorrection rate to the magnitude of the phase error. That is, thecounting rate of the variable sample rate counter62 is variable througha plurality of correction rate steps, as is the variable correction ratecounter 60. However, it is to be understood that the inventioncombination contemplates various alternative, less sophisticated butequally practical servos. For example, in a first alternative, the leveldetector circuit 50 may be omitted and the DC integrator 46 serves as acharging capacitor device, wherein correction is provided via the matrixgates circuit 52 and the program matrixes 56, 58 as the capacitancedischarges. In a further embodiment three programs are provided via thememory program matrix 56; a basic program, a lead program,*and a lagprogram. The latter two programs direct the variable sample rate counter62 up or down respectively at a constant rate. ln the latter embodimentthere is no need for the error count and register unit 54 or for the DCintegrator 46. This latter embodiment corrects for phase error onlyduring the presence of the error and provides the functions of the typeof servo known in the servo art as a pure null-seeking servo."

Referring now to FIGS. 3-6 there is shown in greater detail the logicschematic for the various circuits of F IG. 2, by way of exemplifying apreferred implementation of the invention.

Accordingly, referring first to FIG. 3 in conjunction with FIGS. 4-6,there is shown the phase detector 26, including the reference signalinput and the error signal input of previous mention. Each of thesignals are fed to respective amplifiers 80, 82 which provide similarsquare wave outputs commensurate with the respective reference and errorsignal inputs. The square wave outputs, including any phase error whichmay exist, are introduced to a phase detector circuit 83 formedgenerally of an exclusive OR gate 86, inverters 84, 85 and a pluralityof flip-flops 88. The output from the phase detector 83 consists of twosignals of the same-polarity which are indicative of the lead or lag ofthe error signal relative to the phase of the reference signal. The leadand lag signals are introduced via lines 94, 92 respectively, to adifferential amplifier as a high and low signal of the same polarity.The differential amplifier converts the high and low signals to apositive or negative output signal respectively, which is indicative ofwhether the phase error is leading or lagging the reference signal. Thuswhen lag" line 92 is high, the differential amplifier generates anegative polarity output indicative of a lagging phase error, whereaswhen the lead line 94 is low the differential amplifier provides apositive polarity output indicative of a leading phase error.

The output from the phase detector means 26 is fed to the DC integrator46, which includes a mechanically operable switches 92 having differentpositions whereby capacitors of difierent values may be inserted in thecircuit. The high" position of the switch 92 provides no capacitance andthe output of the amplifier is fed into the DC amplifier 48. The medium"and low settings of the switch 92 insert a small and large capacitance,respectively, into the circuit to provide a selectable slope on thevoltage ramp generated, and thus a different charge rate at which thesubsequent threshold detector will be turned on.

The output from the DC integrator 46 is introduced to a DC amplifier 94which increases the gain of the circuit to thus control the sensitivityof the loop. A rectifier circuit 96 receives the amplified signal andconverts it to a signal having negative values only. Accordingly, thesignal delivered to the level detector circuit 50 is polarityindependent, and the circuit 50 need detect only the magnitude of thevoltage level, not the polarity. Accordingly, the level detector circuit50 provides a plurality of comparators 98 which act as switches.Reference level setting means 100 are provided at each comparator 98input whereby a series of reference levels or voltage thresholds areset. Thus an increasing voltage signal delivered by the DC amplifier 48will successively turn on the comparators 98 as the increasing voltagematches the increasingly higher voltage threshold levels set by thelevel setting means 100. Level A accordingly delivers an outputcorresponding to a percent phase error correction rate, level B a 25percent correction rate, and level C a 50 percent correction rate.

The lead and lag lines 94, 92 respectively are also fed to an OR gate102 which provides an output therefrom when either the lead or the lagsignal exists on lines 94, 92. The output from the OR gate 102 istheerror up count enable signal which is delivered to the error countand register unit 54 of previous mention (shown in greater detail inFIG. 5).

The lead/lag sense signal is generated in the DC amplifier 48, e.g.,amplifier 94, and, as previously described, is a logic signal consistingof either a high or a low, where high indicates a leading phase errorand low indicates a lagging phase error relative to the referencesignal. The lead/lag sense signal is delivered to the matrix gatescircuit 52 shown in further detail in FIG. 4 infra.

The zero state clamp signal previously mentioned with reference to theerror count and register unit 54, and further shown in FIG. 5 infra, isintroduced to the DC integrator 46 (FIG. 3), and particularly to aswitching means which includes a field effect transistor switch means104. The switch means 104 is coupled to the circuit after the switch 92of the DC integrator 46. As previously described, at such time as theerror count and register unit 54 is counted down to zero it generates anoutput consisting of the zero state clamp. The clamp signal is fed tothe field effect transistor switch means 104, whereby the error signalbeing delivered from the phase detector 26 is clamped to ground. Thisresults in the level detector circuit 50 providing the basic program tothe variable sample rate counter 62 via the matrix gates circuit 52 andmemory program matrix 56 indicating a zero phase error in the vibrator14 output.

Referring particularly to FIG. 4 in conjunction with FIGS. 3, 5 and 6,there is shown the matrix gates circuit 52, the memory program matrix56, the variable sample rate counter 62, and basic sample rate counter66 previously discussed in FIG. 2. The voltage levels A, B, C generatedby the level detector 50 of FIG. 3 are introduced to the matrix gatescircuit 52 along with the lead/lag sense signal. Note the latter signalis shown in FIG. 2 as originating in the phase detector 26 for clarityin the block diagram description, but in actuality is generated via theDC amplifier 48 as shown in the detailed schematic of FIG. 3.

The lead/lag sense signal is delivered to a high gain operationalamplifier 106 which acts as a rather sensitive switch. That is, anysmall input triggers the operational amplifier 106 on. Thus a highlead/lag sense signal provides an output of one polarity whereas a lowlead/lag sense signal provides an output from the amplifier 106 of theopposite polarity. The signals are fed to inverter means 108 which inturn provide selection of either a lead or lag" AND-gate means 110, 112respectively. The gates 110, 112 provide a decrease or an increaserespectively of the count delivered by a counter 118 of the variablesample rate counter 62 (via the memory program matrix 56) as determinedby the leading or lagging phase error respectively.

The correction rate is determined by the levels A, B and C which areintroduced to respective AND-gates 114 which, in turn, are coupled viainverters 115 to the lead and lag AND- gate means 110, 112 respectively.As shown, the outputs from the lead and lag gate means 110, 112 aredefined in terms of percent rate of correction of the phase error; thatis, they select a program from the memory program matrix 56 which isshown in FIG. 4 at the matrix gates circuit 52 outputs as, 50, 20 and 5percent decrease in the variable sample rate counter 62 counting rate,or, 5, 20 and 50 percent increase in the counting rate. Note the zerooutput from the matrix gates circuit 52 is provided via an AND-gate 116,coupled at its input to all three outputs of AND-gates 114, and whichprovides a basic program to the variable sample rate counter 62. Thebasic program clocks the counter 62 at the same count rate as that ofthe basic sample rate counter 66, indicating no phase error in thevibrator output.

Accordingly, as shown in FIG. 4 the memory program matrix 56 comprisesseven programs, selectable by the matrix gates circuit 52 outputs,depending upon the magnitude of the phase error and whether it isleading or lagging the phase of the reference signal. To this end, thememory program matrix 56 provides a 20 program for the zero phase erroror basic program, a 21 program which provides a 5 percent decrease inthe rate count, a 25 program for providing a 20 percent decrease in therate count, and a 40 program for a 50 percent decrease in counting rateof the variable sample rate counter 62. Thus for each of the latterthree programs the output of the counter 118 is correspondingly slowedto provide the chosen count rate change to the drive signal unloadcounter 64. Likewise if the phase error is lagging, the lead" gate means112 provide a l9 program for a 5 percent faster count rate to thevariable sample rate counter 62, 21 I5 program for a 20 percentincrease, and a 10 for a 50 percent increase in the rate of correctionof the phase error.

As shown in FIG. 4, the main clock signal of FIG. 2, is fed via terminal72 to the counters 118. The main clock is also fed from terminal 72 tothe series of flip-flops 120 which comprise the basic sample ratecounter 66. The basic count signal shown in FIG. 2 as the counter 66output, is provided via the AND-gate 122, and the AND-gate 124 whereinthe latter acts as an inverter. The basic count output of the counter 66is fed to the memory load counter 68 and provides for loading thememory, and unloading the reference signal from the memory, at aconstant rate. It is to be understood that the main" clock is arelatively wide pulse, as are the basic count and the variable countsignals from the basic and variable sample rate counters 66 and 62respectively. Additional, higher frequency clocks are provided in amanner commonly known in the art, to provide additional functions ofcomponent timing such as, for example, when addressing the memory means32, the A/D and D/A converters 30, 34, 36, the address gates 74, etc.

The output from the matrix gates circuit 52 comprises three outputsignals corresponding to a 5, 20 and 50 percent change in the correctionrate, and are herein shown as outputs 20, 4 and 2 respectively. Theseoutputs are fed to the register program matrix 58.

Referring now to FIG. 5, along with FIGS. 3, 4 and 6, the error countand register unit 54 is coupled to the variable correction rate counter60 and the register program matrix 58.

The error up count enable signal introduced from the phase detector 26,and more particularly the OR-gate 102 thereof, is introduced to anAND-gate 126 which also receives an up clock signal from the basicsample rate counter 66; i.e., the up clock input to the error count andregister unit 54 is the basic count output of the counter 66.Accordingly, when a phase error is present a lead or a lag signal isintroduced to the AND- gate I26 via the OR-gate 102 to enable the formergate. This in turn allows the up clock pulses to pass through the AND-gate 126 to clock a register 128 up only during the period of time thatthe error signal is present. Thus as previously described with referenceto FIG. 2, the register is counted a number of counts equal to theduration of the error pulses delivered by the phase detector 26. Thatis, the counts in the register 128 are equal to the count time of thememory locations in units of memory samples. An AND-gate 130 is coupledto the register 128 locations, whereupon filling the register enablesthe AND-gate 130 to supply a disabling input to the AND-gate 126.Accordingly, a low level from AND-gate 130 prevents further counts fromentering the register 128 via the AND-gate 126, thereby preventing lossof the counts in the register.

As discussed in FIG. 2, the register 128 is counted back down during thephase error correction process at a rate selected by the matrix gatescircuit 52 in response to the level detector circuit 50, and asprogrammed by the register program matrix 58. As may be seen from FIG.5, the matrix 58 provides a 2, a 4, and a 20 program one of which isselected to determine the rate at which the down clock signal isintroduced from a counter 132 to the register 128 via an AND- gate 134.The counter 132 is clocked by the basic count introduced from the basicsample rate counter 66 (FIG. 2), via a gate 135, and a count down enablepulse delivered to the gate 135 and a gate 134. Thus the rate at whichthe register 128 is down clocked is controlled by the matrix programselected by the matrix gates circuit 52 output, which rate is determinedby the particular level at which the level detector circuit 50 isoperating. The AND-gate 134 is always enabled to clock down the register128 as the phase error is being corrected.

A flip-flop 138 is provided and is coupled to the register 128 via anoutput line 139, and provides means for keeping one count in the circuitto allow starting the down clock procedure after the register 128 hasdown clocked to zero. The flip-flop 138 is coupled as one input to theAND-gate 134.

A plurality of gates 140 provide means for sensing when the register 128counts down to zero. At such time they output through an inverter 142 toprovide the zero state clamp signal of previous description in FIGS. 2and 3. The zero state clamp from the gates 140 clears the flip-flop 138.The Wet signal into the register 128 is an initial or master reset forthe system as is conventionally employed in logic systems. This is trueof all the reset and m? signals of the servo 10.

A presettest sweep circuit 144 is coupled to the AND-gate 126. Thiscircuit is associated with the counter preset means 76 coupled to thedrive signal unload counter 64 and previously described with referenceto FIG. 2. That is, the preset test sweep circuit-144 provides the phaseerror in counts during a test sweep survey. which counts are used to setthe counter preset means 76 as further described with reference to FIG.6. Accordingly, the preset test sweep circuit provides logic which looksat the error counts generated by the phase error during the test survey,and then enables the AND gate 126 to display the error counts in theregister 128. The values displayed then can be employed to preset thecounter preset means 76 (FIG. 6). Thus at the start of a seismic surveythe vibrator is operated in phase with the analog input signal.

Referring now to FIG. 6, there is shown the memory load, the referencesignal unload, the the drive signal unload counters 68, 70 and 64respectively, along with the address gates unit 74 and the counterpreset means 76. The counters and address gates are generallyconventional and are shown in logic schematic in FIG. 6 by way ofillustrating their arrangement in addressing the buffer memory means 32.A portion of the address gates unit 74 is shown with a respectivecounter, whereby the outputs from the gates are coupled together and fedto the memory means 32. Means (not shown) are contemplated in theconventional manner for varying the capacity of the memory, as well asfor comparing the memory load counter 68 and the reference unloadcounter 70 to provide synchronization therebetween. The basic count isdelivered from the basic sample rate counter 66 to both the memory loadcounter 68 and the reference signal unload counter 70, at a constantrate, to load the memory means and unload the reference signal with thepreselected delay previously mentioned with reference to FIG. 2. Thevariable count from the variable sample rate counter 62 is introduced tothe drive signal unload counter 64, and additional higher frequencypulses are introduced as,at 146, 148 to enable the respective series ofgates of the address gates unit 74, such signals comprising a driveaddress enable signal and a reference address ena ble signalrespectively. In addition, a load address enable signal of a higherfrequency clock is delivered to 150 to enable the respective series ofgates of the address gates unit 74 associated with the memory loadcounter 68. These higher frequency clocks clock the gates unit duringthe presence of the basic'count clocks as is conventionally done inmemory address logic.

The memory load counter 68 includes a series of flip-flops 152 as shownin FIG. 6 which are employed to vary the capacity of the memory aspreviously mentioned. In addition various reset, and WE signals areintroduced to the various counters as conventionally clone to clear thecounters in preparation for cycling during a subsequent record.

Referring now to the counter preset means 76, the variable count signalis introduced thereto via an inverter 154, flip-flop 156 and an AND-gate158. The output from the AND-gate 158 is delivered via an inverter 160to the counter 162. A series of AND-gates 164 are provided for input ofthe preset information via a plurality of thumbwheels (not shown) whichare set in accordance with the results obtained from the test sweepsurvey previously described with reference to FIG. 5. That is, theexpected phase errors displayed on the register 128 of the error countand register unit 54, during the test sweep survey, are set on theindividual thumbwheels. The latter provide inputs to the counter 162 viathe AND-gates 164. The lead or lag information is-entered by theoperator on the switch means 166, which enables the corresponding one ofa pair of AND-gates 168. Accordingly, in operation, the

counter 162 is clocked via the variable count signal and a higherfrequency clock at 17., until the counter 162 is filled in accordancewith the input set by the thumbwheels. Simultaneously with filling thecounter 162 with the preselected number of counts, the counts are fedvia the respective AND-gate 168 as enabled by the lead/lag switch 166,to place the counts in the drive signal unload counter 64. At such timeas the counter 162 is filled with the prescribed number of counts,outputs therefrom are introduced to an AND-gate 172 which outputs-to theAND-gate 158 and disables the latter. Thus, the drive signal unloadcounter 64 is filled with the prescribed number of counts, whereuponduring a subsequent survey operation the vibrator 14 is driven in phasewith the analog input signal. That is, when the actual survey isstarted, the preset drive signal unload counter 64 is already advancedforward or back to the number of counts corresponding to the phase shifterror previously obtained via the preset test sweep circuit 144 duringthe test sweep survey.

What is claimed is:

1. A digital phase correcting servo for controlling the phase of adriven apparatus relative to the phase of an input signal, comprisingthe combination of:

digital memory means coupled to the input signal and the drivenapparatus for generating a drive signal for introduct ion to the drivenapparatus; said digital memory means including means for providing areference signal which is fixed phase relation, and displaced by aselected time, relative to the input signal:

means coupled to the driven apparatus for detecting any phasedifi'erence between the driven apparatus output and the referencesignal, and for generating an error signal indicative of the phasedifference: and

logic means coupled to the means for detecting and to the digital memorymeans for moving the drive signal introduced to the driven apparatus atime rate of change commensurate with the detected phase difference.

2. The digital phase correcting servo of claim 1 wherein the logic meansdirects the digital memory means to move the drive signal introduced tothe. driven apparatus a number of samples equal to the units of samplerate time corresponding to the detected phase difference, to provide thedriven apparatus output with zero phase difference relative to thereference signal.

3. The digital phase correcting servo of claim 2 wherein the logic meansis adapted to unload the digital memory means at a programmable rate togenerate the corrected drive signal.

4. The digital phase correcting servo of claim 3 wherein the means forgenerating a reference signal includes digital to analog converter meanscoupled to the digital memory means, said reference signal beingunloaded from the digital memory means in response to the logic means ata constant rate relative to the input signal and displaced in timetherefrom on the order of one-half the total memory means locations.

5. The digital phase correcting servo of claim 4 wherein the digitalmemory means includes an analog to digital converter means coupled tothe input signal, a digital memory coupled to the analog to digitalconverter means, a drive and a reference digital to analog convertercoupled to the digital memory, said converters being coupled to thedriven apparatus and to the means for detecting the phase differencerespectively.

6. The digital phase correcting servo of claim 5 wherein means fordetecting comprises phase detector means adapted to generate said errorsignal indicative of the phase difference and of the direction of phaseerror in terms of lead or lag;

said logic means further including program generating means operativelycoupled to the error signal;

said digital memory means being responsive to the program generatingmeans to move the drive signal the detected number of samples therein inthe direction commensurate with the direction of phase error.

7. The digital phase correcting servo of claim 6 wherein the logic meansfurther includes;

an error count and register means operatively coupled to the phasedetector means and adapted to count up and store a number of countscorresponding to the duration of the phase error signal in units ofdigital memory locations;

wherein said program generating means includes at least one programcorresponding to the magnitude of the phase difference and direction ofphase shift, said logic means including means for selectively addressingthe digital memory means in response to the program to direct themovement of the drive signal within the memory means. 8. The digitalphase correcting servo of claim 7 wherein the logic means furtherincludes;

integrator and level detector means coupled to the phase detector meansfor generating at least one voltage level indicative of the magnitude ofthe phase difference;

wherein said program generating means includes matrix gate means adaptedto select a program in responsive to the voltage level; and

counter means coupled to the program generating means and responsive tothe program to clock the digital memory means and move the drive signalthe number of samples corresponding to the phase difference.

9. The digital phase correcting servo of claim 8 wherein the logic meansfurther includes counter presetting means coupled to said counter meansfor presetting the count of the counter means in accordance with themagnitude and direction of phase difference, wherein upon operation ofsaid driven apparatus the drive signal is introduced from the digitalmemory means in phase with the input signal.

1. A digital phase correcting servo for controlling the phase of adriven apparatus relative to the phase of an input signal, comprisingthe combination of: digital memory means coupled to the input signal andthe driven apparatus for generating a drive signal for introduction tothe driven apparatus; said digital memory means including means forproviding a reference signal which is fixed phase Relation, anddisplaced by a selected time, relative to the input signal; meanscoupled to the driven apparatus for detecting any phase differencebetween the driven apparatus output and the reference signal, and forgenerating an error signal indicative of the phase difference; and logicmeans coupled to the means for detecting and to the digital memory meansfor moving the drive signal introduced to the driven apparatus a timerate of change commensurate with the detected phase difference.
 2. Thedigital phase correcting servo of claim 1 wherein the logic meansdirects the digital memory means to move the drive signal introduced tothe driven apparatus a number of samples equal to the units of samplerate time corresponding to the detected phase difference, to provide thedriven apparatus output with zero phase difference relative to thereference signal.
 3. The digital phase correcting servo of claim 2wherein the logic means is adapted to unload the digital memory means ata programmable rate to generate the corrected drive signal.
 4. Thedigital phase correcting servo of claim 3 wherein the means forgenerating a reference signal includes digital to analog converter meanscoupled to the digital memory means, said reference signal beingunloaded from the digital memory means in response to the logic means ata constant rate relative to the input signal and displaced in timetherefrom on the order of one-half the total memory means locations. 5.The digital phase correcting servo of claim 4 wherein the digital memorymeans includes an analog to digital converter means coupled to the inputsignal, a digital memory coupled to the analog to digital convertermeans, a drive and a reference digital to analog converter coupled tothe digital memory, said converters being coupled to the drivenapparatus and to the means for detecting the phase differencerespectively.
 6. The digital phase correcting servo of claim 5 whereinmeans for detecting comprises phase detector means adapted to generatesaid error signal indicative of the phase difference and of thedirection of phase error in terms of lead or lag; said logic meansfurther including program generating means operatively coupled to theerror signal; said digital memory means being responsive to the programgenerating means to move the drive signal the detected number of samplestherein in the direction commensurate with the direction of phase error.7. The digital phase correcting servo of claim 6 wherein the logic meansfurther includes; an error count and register means operatively coupledto the phase detector means and adapted to count up and store a numberof counts corresponding to the duration of the phase error signal inunits of digital memory locations; wherein said program generating meansincludes at least one program corresponding to the magnitude of thephase difference and direction of phase shift, said logic meansincluding means for selectively addressing the digital memory means inresponse to the program to direct the movement of the drive signalwithin the memory means.
 8. The digital phase correcting servo of claim7 wherein the logic means further includes; integrator and leveldetector means coupled to the phase detector means for generating atleast one voltage level indicative of the magnitude of the phasedifference; wherein said program generating means includes matrix gatemeans adapted to select a program in responsive to the voltage level;and counter means coupled to the program generating means and responsiveto the program to clock the digital memory means and move the drivesignal the number of samples corresponding to the phase difference. 9.The digital phase correcting servo of claim 8 wherein the logic meansfurther includes counter presetting means coupled to said counter meansfor presetting the count of the counter means in accordance with themagnitude and direction of phase difference, wherein upon oPeration ofsaid driven apparatus the drive signal is introduced from the digitalmemory means in phase with the input signal.